1. Field of the Invention
The present invention relates generally to an electrostatic discharge (ESD) protection apparatus and method, and more particularly, to a smaller and more efficient protection device embodying a semiconductor-controlled or silicon-controlled rectifier (SCR) with a programmable holding voltage.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
As is well-known in the microelectronics industry, integrated circuit devices are susceptible to damage from application of excessive voltages, such as electrostatic discharge (ESD) events. During an ESD event, charge transferred within a circuit can develop voltages that are large enough to breakdown insulating films, such as gate oxides, on the device. Alternatively, the charge can dissipate significant energy to cause electro-thermal failures in the device itself.
An ESD event can arise from handling a packaged integrated circuit, where charge is transferred from the external environment to an input/output (I/O) pad of the integrated circuit. The charge transfer can occur in a time typically less than 1 microsecond, which is sufficient time to breakdown the insulating films, or contacts, of transistors coupled to the I/O pad. Another type of ESD event involves “hot socket insertion.” For example, the integrated circuit may be used in a mixed-voltage environment, where the integrated circuit may operate at one voltage level, but must interface with another integrated circuit operating at a different, possibly higher voltage level. The dissimilar supply voltage levels cause charge to be applied on the I/O pad whenever the integrated circuit is inserted into a board or chipset having a higher supply voltage. In addition to impeding charge from the environment or via hot socket insertion, there are many other well-known examples of ESD events, all of which apply voltage exceeding, by many orders of magnitude, the normal (or nominal) supply voltage of the integrated circuit. Any such ESD event which is intermittent and more than maybe 20-50% of the normal operating parameters of the integrated circuit can be classified as “excessive voltage” arising from an ESD event.
There are numerous ways in which to protect the integrated circuit when an ESD event occurs. For example, a clamp can be used to shunt the incoming voltage on the I/O pad within a desired window that is tolerable to the integrated circuit. A popular clamping device can include a diode between the I/O pad and the power and supply conductors. When an ESD event occurs, the positive or negative polarity ESD voltage will be shunted to the positive or negative power and ground supplies, respectively. Unfortunately, however, this causes undue fluctuation on the power and/or ground supply conductors, which then measurably impacts the operation and reliability of all circuits connected thereto.
Another approach that can be used is to apply a silicon-controlled rectifier or semiconductor-controlled rectifier (SCR) circuit between the I/O pad and a ground supply conductor for shunting away positive or negative polarity ESD voltages. While progress has been made in the development of SCR-based circuits, fast ESD events, such as those described in Charged Device Model (CDM), have uncovered weaknesses in at least some of the known SCR-based ESD protection circuits. Moreover, many SCR circuits require a field-effect transistor (FET) for controlling the SCR. When the ESD event occurs, the junction formed by the drain of the FET and its corresponding substrate breaks down under high reverse bias voltage, thereby causing the first of a pair of transistors within the SCR to turn on. The addition of a third FET above and beyond the feedback-coupled pair of transistors of the SCR increases the overall footprint or geometric size of the protection device. As geometries continue to shrink and the area demands on the integrated circuit increase, requiring a third transistor proves not only inefficient, but unreliable when depending on a consistent breakdown of that transistor for triggering forward conduction of the SCR.
Accordingly, there is a need to provide an improved ESD protection circuit suitable not only for use in the integrated circuit, but also one that has minimum footprint, is more accurate as to its holding voltage, and yet maintains tighter control of the power and ground supply voltages applied to the power and ground conductors during an ESD event and after the event subsides.